定制写作代写服务成功案例
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EEE335/EEE348: 2024-2025 Digital Coursework.
2024-2025 Digital Coursework.
项目类别：电气电力工程
The Task
Your task is to design a CMOS logic gate to implement the logic function below (based on the last digit of
your student Number, simulate it in LTSPICE and assess its performance.
Last Digit of Student Number Logic Function
Even
𝑌 = 𝐵.(𝐶̅
+ 𝐷.𝐸)
Odd
𝑌 = 𝐶̅
.(𝐵 + 𝐷 + 𝐸)
You should implement your design within the basic spice design file that accompanies this assignment (Digital
Spice Design Template.asc). This provides a framework that you should use and into which you should insert
your circuit. It contains four voltage sources which generate sequences of pulses (for generating the four
inputs to your circuit: A…D). The outputs from these voltage sources pass through two minimum sized
inverters (so the outputs are more realistic). The waveforms from the voltage sources approximate to a binary
number “DCBA” and cycles from 0000 to 1111, etc. across a 5s period. There are small offsets of 5ns between
each of the waveforms to make them more interesting. You are free to change the sequences of values applied
to your circuit (to allow you to answer some of the questions). However, there are certain instances when the
sequence of inputs you use MUST be the ones supplied in the template.
The outputs of the four pairs of inverters are labelled A, B, C, D. These MUST be the only inputs that you drive
into your circuit for the function that you are implementing. You cannot use the outputs from the voltage
sources or any of the outputs from the first inverter in each pair.
The output of the function, Y, from the circuit you implement is connected to a 100fF capacitor (this is also in
the basic spice design template file).
To reiterate, you should only connect your circuit to VDD, GND, A, B, C, D, and Y in the basic design file
template. You will note that Vsupp is a parameter in the set of directives and it is set, currently, to 3.3V. This
is used to generate VDD (which you will use in your circuit), Vdriver (which is used, separately, to supply the
inverters that generate A, B, C, and D), and the pulse voltages generated in V1, V2, V3, and V4. You can change
Vsupp in the directive and all the voltages generated will change together. You should not need to create any
new voltage sources to complete this task.
The transistors in your design should be taken from the 5827_035 library. The logic function must be
decomposed into a core circuit with input and/or output inverters as required. Decomposing the logic function
into a cascade of two input standard logic gates will gain NO marks.
The circuit you design should try to optimise the area and performance of your circuit:
1. Area is, essentially, the W*L for all the transistors in your design (do not include M1..M16 in your
estimation of Area);
2. Time should be measured as the worst-case time between any of the inputs passing switching voltage
(VDD/2) either rising or falling and the output voltage passing the same (VDD/2) as a direct
consequence of the change of input voltage.
You will need to submit a report (maximum 5 pages, 11pt text, normal margins) to include the following:
• A clearly labelled diagram of your circuit design from SPICE, and a short description of it. You do not
need to include the voltage generators but the signals going into and out from your actual design
should be labelled (please make sure that any text on it is readable).
• A justification that your design meets the specifications. Please ensure that you include the sizing of the
transistors.
• A plot of the propagation delay (Time) between the A input and the Y output as the power supply
voltage, VDD, is varied between 0.9V and 3.3V (in steps of 100mV). HINT: you need to ensure
that Y is changing ONLY as a consequence of a change in A.
• A plot of the energy consumed by your circuit over the 5us period of the simulation as the power
supply voltage, VDD, is varied between 0.9V and 3.3V (in steps of 100mV). You will need to think
carefully about how to measure the energy going into your circuit. You MUST use the input
waveforms, as supplied, for this exercise.
As well as submitting the report, you also need to submit a functioning LTSpice schematic file (this does not
form part of the assessment but I may simulate your schematic if I think there is an issue).
Please, also, quote the last 3 digits of your Student Number in your report.
