Organization of Digital Computers Lab

EECS112L

Fall 2024

Lab 1 (100 Points)

In this lab, you are given an arithmetic logic unit (ALU) design, which you are to test. The design has some bugs in it. You will design a testbench to test the functions of the ALU to find the bugs. You will also revise the sequential logic (D flip-flops) and create testbench for it.

1 ALU Overview

An ALU performs basic arithmetic and logic operations. Examples of arithmetic operations are addition, subtraction, multiplication, and division. Examples of logic operations are comparisons of values ,such as NOT, AND, and OR. This ALU has 2 4-bit inputs A and B for operands, a 4-bit input ALU_Sel for selecting the operation, a 4-bit output ALU_Out, and a 1-bit output CarryOut. The datapath is just 4-bits wide to allow for easy coverage testing of the different operations. The operations of the ALU are specified in the table below.

ALU_Sel ALU Operation

0000 ALU ut = A + B

0001 ALU ut = A - B

0010 ALU ut = A * B

0011 ALU ut = A / B

0100 ALU ut = A << 1

0101 ALU ut = A >> 1

0110 ALU ut = A rotated left by 1

0111 ALU ut = A rotated right by 1

1000ALU ut = A and B

1001 ALU ut = A or B

1010ALU ut = A xor B

1011 ALU ut = A nor B

1100 ALU ut = A nand B

1101 ALU ut = A xnor B

1110 ALU ut = 1 if A>B else 0

1111 ALU ut = 1 if A=B else 0

Note: Check canvas for some review slides on Verilog operators.

Below you see the Verilog code for the ALU. Create a new Vivado project and copy this code to a file named alu.v.

Code 1: 4-bit ALU.

module alu ( input [3:0] A,B, // ALU 4- bit Inputs input [3:0] ALU_Sel ,// ALU Selection output [3:0] ALU_Out , // ALU 4- bit Output output CarryOut // Carry Out Flag ); reg [7:0] ALU_Result ; wire [4:0] tmp ; assign ALU_Out = ALU_Result ; // ALU out assign tmp = {1’b0 ,A} + {1’b0 ,B}; assign CarryOut = tmp [4]; // Carryout flag always @ (*) begin case ( ALU_Sel ) 4’ b0000 : // Addition ALU_Result = A + B; 4’ b0001 : // Subtraction ALU_Result = A - B; 4’ b0010 : // Multiplication ALU_Result = A ** B; 4’ b0011 : // Division ALU_Result = A/B; 4’ b0100 : // Logical shift left ALU_Result = A <=1; 4’ b0101 : // Logical shift right ALU_Result = A > >1; 4’ b0110 : // Rotate left ALU_Result = {A [2:0] , A [3]}; 4’ b0111 : // Rotate right ALU_Result = {A[3] ,A [3:1]}; 4’ b1000 : // Logical and ALU_Result = A && B; 4’ b1001 : // Logical or ALU_Result = A || B; 4’ b1010 : // Bitwise xor ALU_Result = A ? B; 4’ b1011 : // Logical nor ALU_Result = ～(A || B); 4’ b1100 : // Logical nand ALU_Result = ～(A && B); 4’ b1101 : // Bitwise xnor ALU_Result = ～ (A ? B); 4’ b1110 : // Greater comparison ALU_Result = (A>B) ? 4’b0 : 4’b1; 4’ b1111 : // Equal comparison ALU_Result = (A==B) ? 4’b1 : 4’b0; default : ALU_Result = A + B; endcase end endmodule