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CE 100 Schlag DO NOT SAVE or PRINT Sample Final 1
12. (12 points)
Below is the datapath for a sequential system which computes the arithmetic mean of the squares
of sixteen 8-bit binary integers. The 8-bit integers are inputs to a multiplexer whose selectors are
tied to a 4-bit counter. (This is similar to the problem on Homework 6, except that now the integers
are first squared before they are added up.)
The system computes the mean of the squares by first clearing the total (held in Register)
and then multiplying each 8-bit binary integer by itself and adding the result to the contents of the
register. The total in the register is divided by 16 by removing the lower 4 bits.
If Multiply’s start input (StartMult) is high on the clock edge the multiplication of the two
8-bit integers on its inputs A and B begins. The multiplication may take several clock cycles. The
16-bit result appears on the output whenMultiply’s Done output (MultDone) is high. Multiply
holds its result and MultDone will remain high until the next clock edge where the start input is
high. The inputs A and B must remain valid during the multiplication, that is, until MultDone
goes high.
S
. . .
888
0 1 2 15
8
MUX 16 by 8
R
CE
Register
Total[19:0]
16
Clear
Load
CLK
20
+
CLK Done
Start
Multiply
TC
CE
Inc
CLK
Q 4CNT4
Last
20
20
Total[19:4] Out[15:0]
A B
Data Inputs
StartMult
MultDone
8
CE 100 Schlag DO NOT SAVE or PRINT Sample Final 2
(Problem 12 continued)
Design the control for the squares mean computation (SQMEAN CONTROL). Note that
SQMEAN CONTROL has a Start input which tells it when to begin the computation and a Done
output which it asserts when it is finished (the result is ready). The result of the computation must
be held in Register until the next Start signal is received.
CLK
MultDone
StartMult
Last
Start Inc
Load
Clear
Done
CONTROL
SQMEAN
You may assume the counter (CNT4) is initially at 0, but you must return it to 0 before asserting
Done so that it is ready for the next computation; there is no other way to reset CNT4.
a. Draw the state diagram for SQMEAN CONTROL.
b. Give the state transition table (see next page) for your state machine.
c. Obtain the next-state and output equations for your state machine assuming a one-hot state
encoding.
LOAD
CHILLIN
Done
MULT
MultDone
Start/Clear,StartMult
Start MultDone & Last / Load, Inc1/StartMult
MultDone & Last / Load, Inc
CE 100 Schlag DO NOT SAVE or PRINT Sample Final 3
(extra space for Problem 12)
State Transition Table
Present Inputs Next Outputs
State Start Last MultDone State Inc Load Clear StartMult Done
CHILLIN 0 – – CHILLIN 0 0 0 0 1
CHILLIN 1 – – MULT 0 0 1 1 1
MULT – – 0 MULT 0 0 0 0 0
MULT – 0 1 LOAD 1 1 0 0 0
MULT – 1 1 CHILLIN 1 1 0 0 0
LOAD – – – MULT 0 0 0 1 0
There are no DON’T CARE conditions for the outputs since we need to control the counter’s value
and the register’s value at all times. We also need to keep the multiplier idle in state CHILLIN so
that it is ready when needed.
next CHILLIN = Start · CHILLIN + Last · MultDone · MULT
next MULT = Start · CHILLIN +MultDone · MULT+ LOAD
next LOAD = Last · MultDone · MULT
Inc = MultDone · MULT
Load = Inc
Done = CHILLIN
Clear = Start · CHILLIN
StartMult = Start · CHILLIN + LOAD
